The semiconductor integrated circuit industry has experienced rapid growth in the past several decades. Technological advances in semiconductor materials and design have produced increasingly smaller and more complex circuits. These material and design advances have been made possible as the technologies related to processing and manufacturing have also undergone technical advances. In the course of semiconductor evolution, the number of interconnected devices per unit of area has increased as the size of the smallest component that can be reliably created has decreased.
A semiconductor wafer is processed by a semiconductor manufacturer to form various integrated circuits (IC) in different regions of the wafer. The wafer includes a substrate with many patterned material layers thereon that form the discrete devices that make up a circuit. Variations in pattern density over the different regions can cause various issues including critical dimension (CD) variation or CD uniformity. As the node or scale of the semiconductor fabrication decreases to advanced technologies, such as from 45 nm to 32 nm and to 28 nm, the functionalities of an IC device are more sensitive to the CD variations and uniformity. For example, dense lines and isolated lines are common in IC layout and cannot be avoided by the design rules. However, as the feature size decreases, high fidelity replication of such mask features into an underlying material layer can be problematic. Additionally, as the technologies have advanced, some currently use approaches may have limited effectiveness and applicability. Therefore, there is a need of methods to address such issues.
These figures will be better understood by reference to the following detailed description.